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An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication., , and . ISCAS (5), page 361-364. IEEE, (2003)An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates., and . IEEE Trans. Very Large Scale Integr. Syst., 14 (9): 975-985 (2006)Average-case technology mapping of asynchronous burst-mode circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (10): 1418-1434 (1999)Sibling-substitution-based BDD minimization using don't cares., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (1): 44-55 (2000)Implicit enumeration of strongly connected components and anapplication to formal verification., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (10): 1225-1230 (2000)Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (4): 979-992 (2022)When Bio-Inspired Computing meets Deep Learning: Low-Latency, Accurate, & Energy-Efficient Spiking Neural Networks from Artificial Neural Networks., , , , and . CoRR, (2023)Spiking Neural Networks with Dynamic Time Steps for Vision Transformers., , , and . CoRR, (2023)Toward High Performance, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ., , , and . CoRR, (2024)Linearizing Models for Efficient yet Robust Private Inference., , and . CoRR, (2024)