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Theory, Analysis and Implementation of an On-Line BIST Technique., and . VLSI Design, 1 (1): 9-22 (1993)Easily Testable Two-Dimensional Cellular Logic Arrays., and . IEEE Trans. Computers, 23 (11): 1204-1207 (1974)An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling., and . J. Electron. Test., 30 (5): 569-580 (2014)Analysis and test procedures for NOR flash memory defects., and . Microelectron. Reliab., 48 (5): 698-709 (2008)Delay Fault Testing of Processor Cores in Functional Mode., , , and . IEICE Trans. Inf. Syst., 88-D (3): 610-618 (2005)Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment., , , and . IEICE Trans. Inf. Syst., 96-D (6): 1323-1331 (2013)Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools., , , , and . IEICE Trans. Inf. Syst., 91-D (3): 690-699 (2008)Routing TCP Flows in Underwater Mesh Networks., , and . IEEE J. Sel. Areas Commun., 29 (10): 2022-2032 (2011)A Tutorial on Built-In Self-Test, Part 2: Applications., , and . IEEE Des. Test Comput., 10 (2): 69-77 (1993)