Author of the publication

Analysis and test procedures for NOR flash memory defects.

, and . Microelectron. Reliab., 48 (5): 698-709 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity., , and . VLSI Design, page 100-107. IEEE Computer Society, (2006)Testing Flash Memories for Tunnel Oxide Defects., and . VLSI Design, page 157-162. IEEE Computer Society, (2008)Techniques for Disturb Fault Collapsing., and . J. Electron. Test., 23 (4): 363-368 (2007)Analysis and test procedures for NOR flash memory defects., and . Microelectron. Reliab., 48 (5): 698-709 (2008)Fault model and test procedure for phase change memory.. IET Comput. Digit. Tech., 5 (4): 263-270 (2011)Switched positive/negative charge pump design using standard CMOS transistors., , and . IET Circuits Devices Syst., 4 (1): 57-66 (2010)Fault collapsing for flash memory disturb faults., and . ETS, page 142-147. IEEE Computer Society, (2005)Flash Memory Disturbances: Modeling and Test., and . VTS, page 218-224. IEEE Computer Society, (2001)Optimizing program disturb fault tests using defect-based testing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (6): 905-915 (2005)Switched Polarity Charge Pump for NOR-type Flash Memories., , and . ICECS, page 1200-1203. IEEE, (2006)