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Disambiguation of "Lee, Tai-Cheng"

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/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis.

, , and . ICCAD, page 159:1-159:8. IEEE, (2020)

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Tai Cheng Hsueh

Chun-Tai Lee

Cheng-Chieh Lee

Cheng-San Lee

Cheng-Yung Cheng

 

Other publications of authors with the same name

Generation of random non-overlapping dot patterns for light guides using molecular dynamics simulations with variable r-cut and reflective boundary techniques., , , and . Comput. Phys. Commun., 177 (11): 851-862 (2007)A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation., and . ISSCC, page 514-515. IEEE, (2008)Jitter error cancellation technique in digital domain for ADC., and . VLSI-DAT, page 1-4. IEEE, (2013)An all-digital de-skew clock generator for arbitrary wide range delay., , , and . APCCAS, page 112-115. IEEE, (2010)A technique for in-band phase noise reduction in fractional-N frequency synthesizers., and . A-SSCC, page 273-276. IEEE, (2016)A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier., , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (4): 2021-2025 (2022)A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator., and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (5): 1264-1273 (2013)Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs., , , , , , , , and . ISQED, page 1-6. IEEE, (2022)An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique., , , and . A-SSCC, page 53-56. IEEE, (2017)The Design and Analysis of Dual-Delay-Path Ring Oscillators., and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (3): 470-478 (2011)