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Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects.

, , , , and . ATS, page 131-136. IEEE Computer Society, (2014)

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Guaranteed convergence in a class of Hopfield networks., , and . IEEE Trans. Neural Networks, 3 (6): 951-961 (1992)Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design., , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (4): 42:1-42:19 (2019)Correcting Unidirectional Errors with Nonpositive Hopfield Networks., , and . ICNN, page 2933-2938. IEEE, (1995)Universal delay test sets for logic networks., , and . IEEE Trans. Very Large Scale Integr. Syst., 7 (2): 156-166 (1999)Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines., , , , and . DATE, page 1022-1027. IEEE, (2019)Selection of a fault model for fault diagnosis based on unique responses., and . DATE, page 994-999. IEEE, (2009)A supervised machine learning application in volume diagnosis., , , , , , and . ETS, page 1-6. IEEE, (2019)Volume diagnosis data mining., , and . ETS, page 1-10. IEEE, (2017)Input test data volume reduction based on test vector chains., and . European Test Symposium, page 240. IEEE Computer Society, (2010)Test vector chains for increased targeted and untargeted fault coverage., and . ASP-DAC, page 663-666. IEEE, (2008)