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14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology.

M. Song, T. Kim, J. Kim, W. Kim, S. Kim, and H. Park. ISSCC, page 1-3. IEEE, (2015)

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F Himmel

F Kessler

F Beyer

F Arndt

F Röpke

Other publications of authors with the same name

A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology.K. Choo, H. Kim, W. Kim, J. Kim, T. Kim, and H. Ko. ISSCC, page 120-122. IEEE, (2018)A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology.K. Choo, S. Kim, W. Kim, J. Kim, T. Kim, and H. Park. CICC, page 1-4. IEEE, (2014)A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.J. Hong, S. Kim, J. Liu, N. Xing, T. Jang, J. Park, J. Kim, T. Kim, and H. Park. ISSCC, page 240-242. IEEE, (2012)14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology.M. Song, T. Kim, J. Kim, W. Kim, S. Kim, and H. Park. ISSCC, page 1-3. IEEE, (2015)A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.W. Kim, J. Park, J. Kim, T. Kim, H. Park, and D. Jeong. ISSCC, page 250-251. IEEE, (2013)PAIDB v2.0: exploration and analysis of pathogenicity and resistance islands.S. Yoon, Y. Park, and J. Kim. Nucleic Acids Res., 43 (Database-Issue): 624-630 (2015)Ensemble learning of genetic networks from time-series expression data.D. Nam, S. Yoon, and J. Kim. Bioinform., 23 (23): 3225-3231 (2007)A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.T. Jang, N. Xing, F. Liu, J. Shin, H. Ryu, J. Kim, T. Kim, J. Park, and H. Park. ISSCC, page 254-255. IEEE, (2013)15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology.S. Kim, W. Kim, M. Song, J. Kim, T. Kim, and H. Park. ISSCC, page 1-3. IEEE, (2015)CFGP: a web-based, comparative fungal genomics platform.J. Park, B. Park, K. Jung, S. Jang, K. Yu, J. Choi, S. Kong, J. Park, S. Kim, H. Kim and 6 other author(s). Nucleic Acids Res., 36 (Database-Issue): 562-571 (2008)

BibSonomy

Disambiguation of "Kim, Jihyun F."