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A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 809-817 (2011)A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks., and . IEEE Trans. Parallel Distributed Syst., 6 (5): 482-497 (1995)Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router., , , , and . IEEE Trans. Parallel Distributed Syst., 16 (11): 1009-1021 (2005)Dynamically Configurable Message Flow Control for Fault-Tolerant Routing., , and . IEEE Trans. Parallel Distributed Syst., 10 (1): 7-22 (1999)Formulation of parallel image processing tasks., and . Pattern Recognit. Lett., 2 (4): 261-270 (1984)Parallel image normalization on a mesh connected array processor., , and . Pattern Recognit., 20 (1): 115-124 (1987)NeuroTrainer: An Intelligent Memory Module for Deep Learning Training., , , and . CoRR, (2017)Using rapid prototyping in computer architecture design laboratories., , , and . WCAE@HPCA, page 4. ACM, (1996)Interconnection networks - an engineering approach., , and . IEEE, (1997)Switching Techniques.. Encyclopedia of Parallel Computing, Springer, (2011)