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Critical hazard free test generation for asynchronous circuits., and . VTS, page 203-209. IEEE Computer Society, (1997)A new methodology for improved tester utilization., , , , , and . ITC, page 916-923. IEEE Computer Society, (2001)Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits., , , and . J. Electron. Test., 19 (2): 125-135 (2003)A Behavioral Fault Simulator for Ideal., , , and . IEEE Des. Test Comput., 9 (4): 14-21 (1992)Packet-Based Input Test Data Compression Techniques., , and . ITC, page 154-163. IEEE Computer Society, (2002)A Tutorial on STDF Fail Datalog Standard., , , and . ITC, page 1-10. IEEE Computer Society, (2008)DFT for fast testing of self-timed control circuits., , and . Asian Test Symposium, page 382-386. IEEE Computer Society, (1995)Testing self-timed circuits using partial scan., and . ASYNC, page 160-169. IEEE Computer Society, (1995)Panel Summaries: Real-Time Volume Diagnostics--Requirements and Challenges.. IEEE Des. Test Comput., 23 (4): 315 (2006)Test Vector Compression Using EDA-ATE Synergies., , , and . VTS, page 97-102. IEEE Computer Society, (2002)