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A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

R. Farjad-Rad, A. Nguyen, J. Tran, T. Greer, J. Poulton, W. Dally, J. Edmondson, R. Senthinathan, R. Rathi, M. Lee, and H. Ng. IEEE J. Solid State Circuits, 39 (9): 1553-1561 (2004)

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Involvement of Lgl and Mahjong/VprBP in Cell CompetitionY. Tamori, C. Bialucha, A. Tian, M. Kajita, Y. Huang, M. Norman, N. Harrison, J. Poulton, K. Ivanovitch, L. Disch and 3 other author(s). PLoS Biol, 8 (7): e1000422+ (Jul 13, 2010)A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS.J. Poulton, R. Palmer, A. Fuller, T. Greer, J. Eyles, W. Dally, and M. Horowitz. IEEE J. Solid State Circuits, 42 (12): 2745-2757 (2007)PixelFlow: high-speed rendering using image composition.S. Molnar, J. Eyles, and J. Poulton. SIGGRAPH, page 231-240. ACM, (1992)Pixel-Planes 4: A Summary.J. Eyles, J. Austin, H. Fuchs, T. Greer, and J. Poulton. Advances in Computer Graphics Hardware, page 183-207. Springer, (1987)PixelFlow: The Realization.J. Eyles, S. Molnar, J. Poulton, T. Greer, A. Lastra, N. England, and L. Westover. Workshop on Graphics Hardware, page 57-67. The Eurographics Association, (1997)A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.S. Song, J. Poulton, X. Chen, B. Zimmer, S. Tell, W. Turner, S. Kudva, N. Nedovic, J. Wilson, C. Gray and 1 other author(s). CICC, page 1-4. IEEE, (2019)A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.B. Leibowitz, R. Palmer, J. Poulton, Y. Frans, S. Li, J. Wilson, M. Bucher, A. Fuller, J. Eyles, M. Aleksic and 2 other author(s). IEEE J. Solid State Circuits, 45 (4): 889-898 (2010)A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.R. Farjad-Rad, A. Nguyen, J. Tran, T. Greer, J. Poulton, W. Dally, J. Edmondson, R. Senthinathan, R. Rathi, M. Lee and 1 other author(s). IEEE J. Solid State Circuits, 39 (9): 1553-1561 (2004)Jitter transfer characteristics of delay-locked loops - theories and design techniques.M. Lee, W. Dally, T. Greer, H. Ng, R. Farjad-Rad, J. Poulton, and R. Senthinathan. IEEE J. Solid State Circuits, 38 (4): 614-621 (2003)Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-Planes.H. Fuchs, J. Goldfeather, J. Hultquist, S. Spach, J. Austin, F. Jr., J. Eyles, and J. Poulton. Advances in Computer Graphics, page 169-187. Springer, (1985)

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A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

Please choose a person to relate this publication to

Roswitha John

Shincy John

Daniel Johnen

Anita John

Tina John

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Poulton, John"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

Please choose a person to relate this publication to

Roswitha John

Shincy John

Daniel Johnen

Anita John

Tina John

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
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A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.