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Disambiguation of "Lee, Ming-Ju Edward"

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A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 39 (9): 1553-1561 (2004)

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Ju-Hyoung Lee

Hyuk Ju Lee

Hyuk Ju Lee

Ju-Bong Lee

Seong-Ju Lee

 

Other publications of authors with the same name

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 39 (9): 1553-1561 (2004)Jitter transfer characteristics of delay-locked loops - theories and design techniques., , , , , , and . IEEE J. Solid State Circuits, 38 (4): 614-621 (2003)A 15-22 Gbps Serial Link in 28 nm CMOS With Direct DFE., , , , , , , and . IEEE J. Solid State Circuits, 49 (12): 3104-3115 (2014)26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 438-439. IEEE, (2014)CMOS High-Speed I/Os - Present and Future., , , , , , and . ICCD, page 454-461. IEEE Computer Society, (2003)A 20-Gb/s 0.13-μm CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer., , , , , and . IEEE J. Solid State Circuits, 40 (4): 1004-1011 (2005)A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips., , , , , , and . IEEE J. Solid State Circuits, 37 (12): 1804-1812 (2002)A second-order semidigital clock recovery circuit based on injection locking., , , , , , , , and . IEEE J. Solid State Circuits, 38 (12): 2101-2110 (2003)Low-power area-efficient high-speed I/O circuit techniques., , and . IEEE J. Solid State Circuits, 35 (11): 1591-1599 (2000)A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os., , , , , , , , , and 1 other author(s). CICC, page 77-80. IEEE, (2003)