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Disambiguation of "Bagherzadeh, Nader"

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Design and Implementation of the MorphoSys Reconfigurable Computing Processor.

, , , , , , and . VLSI Signal Processing, 24 (2-3): 147-164 (2000)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hassan Bagherzadeh

Faramarz Nader

Nader Tawassoli

Nader Purnaqchéband

Nader Ahmad

 

Other publications of authors with the same name

Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks., , , , and . IEEE Trans. Computers, 68 (5): 660-675 (2019)Software Authorization Systems., , , and . IEEE Software, 3 (5): 34-41 (1986)A Routing and Broadcasting Scheme on Faulty Star Graphs., , and . IEEE Trans. Computers, 42 (11): 1398-1403 (1993)Embedding an Arbitrary Binary Tree into the Star Graph., , and . IEEE Trans. Computers, 45 (4): 475-481 (1996)Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform., , , and . SoCC, page 3-6. IEEE, (2004)Network Facility for a Reconfigurable Computer Architecture., , , , and . ICDCS, page 264-271. IEEE Computer Society, (1985)Design and Implementation of the MorphoSys Reconfigurable Computing Processor., , , , , , and . VLSI Signal Processing, 24 (2-3): 147-164 (2000)A formal approach to context scheduling for multicontext reconfigurable architectures., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (1): 173-185 (2001)A framework for reconfigurable computing: task scheduling and context management., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 858-873 (2001)IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes., , and . Microprocess. Microsystems, (2020)