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Disambiguation of "Sinha, Sharad"

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DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis.

, , , and . ICFPT, page 300-301. IEEE, (2023)

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Prashant Sinha

Intermediate states in bivalent ion induced shrinking of polyacrylate coils on surfaces and in solution. TU Dresden, (2009)

Sharad Chandra

Sharad Prasad

Vineet Sinha

Jyoti Sinha

 

Other publications of authors with the same name

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2279-2292 (2021)Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation., , and . IEEE Trans. Computers, 72 (7): 1886-1900 (July 2023)YOLORe-IDNet: An Efficient Multi-Camera System for Person-Tracking., , and . CoRR, (2023)Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective., and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 5:1-5:18 (2014)Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA., , and . FCCM, page 172-180. IEEE, (2019)Decision tree based hardware power monitoring for run time dynamic power management in FPGA., , and . FPL, page 1-8. IEEE, (2017)Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis., and . Int. J. Reconfigurable Comput., (2014)An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power., , and . CoRR, (2020)FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs., , , , and . FPGA, page 15-25. ACM, (2023)Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict., , , and . DAC, page 979-984. IEEE, (2021)