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The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.

, , , , , , , , , , , , , , , , , , , , , , и . IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)

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Alfons Restle

David Restle

Wilhelm Restle

Konstantin Restle

Markus Restle

 

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A Resonant Global Clock Distribution for the Cell Broadband Engine Processor., , , , , , , , , и . IEEE J. Solid State Circuits, 44 (1): 64-72 (2009)Loop-based interconnect modeling and optimization approach for multigigahertz clock network design., , , , , и . IEEE J. Solid State Circuits, 38 (3): 457-463 (2003)Design of Resonant Global Clock Distributions., , и . ICCD, стр. 248-253. IEEE Computer Society, (2003)New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems., и . ASYNC, IEEE Computer Society, (2005)Loop-based interconnect modeling and optimization approach for multi-GHz clock network design., , , , и . CICC, стр. 19-22. IEEE, (2002)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 96-97. IEEE, (2014)Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor., , , , , , , , и . ISSCC, стр. 1-3. IEEE, (2022)The circuit and physical design of the POWER4 microprocessor., , , , , , , , и . IBM J. Res. Dev., 46 (1): 27-52 (2002)Subtractive Router for Tree-Driven-Grid Clocks., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (6): 868-877 (2012)Deterministic Frequency and Voltage Enhancements on the POWER10 Processor., , , , , , , , и . IEEE J. Solid State Circuits, 58 (1): 102-110 (2023)