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Disambiguation of "Muresan, Valentin"

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Power-Constrained Block-Test List Scheduling.

, , , and . IEEE International Workshop on Rapid System Prototyping, page 182-187. IEEE Computer Society, (2000)

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Remus Muresan

Adrian Muresan

Gheorghe Muresan

Liana Maria Muresan

Nicoleta Mihaela Muresan

 

Other publications of authors with the same name

Requirements of a real-time multiprocessor operating system for multimedia applications., , , , and . SACI, page 209-215. IEEE, (2011)FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator., , , and . FPT, page 317-318. IEEE, (2005)A comparison of classical scheduling approaches in power-constrained block-test scheduling., , , and . ITC, page 882-891. IEEE Computer Society, (2000)The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints., , , and . VTS, page 417-422. IEEE Computer Society, (2000)Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints., , , and . J. Electron. Test., 20 (1): 61-78 (2004)Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling., , , and . Asian Test Symposium, page 465-470. IEEE Computer Society, (2000)Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints., , , and . IEEE International Workshop on Rapid System Prototyping, page 162-167. IEEE Computer Society, (2001)Energy-Efficient Hardware Architecture for Variable N-point 1D DCT., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 780-788. Springer, (2004)Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm., , and . EvoWorkshops, volume 3907 of Lecture Notes in Computer Science, page 296-307. Springer, (2006)An Efficient Hardware Architecture for a Neural Network Activation Function Generator., , , and . ISNN (2), volume 3973 of Lecture Notes in Computer Science, page 1319-1327. Springer, (2006)