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An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video., , , , , and . Sci. China Inf. Sci., 56 (7): 1-14 (2013)Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints., , , , , and . Sci. China Inf. Sci., 58 (8): 1-14 (2015)MapReduce inspired loop mapping for coarse-grained reconfigurable architecture., , , and . Sci. China Inf. Sci., 57 (12): 1-14 (2014)Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution., , , , and . IEEE Comput. Archit. Lett., 17 (2): 147-150 (2018)An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS., , , , , , and . VLSI Circuits, page 37-38. IEEE, (2018)A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)., , , , and . FPGA, page 270. ACM, (2015)Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3081-3094 (2018)Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (12): 2271-2283 (2019)Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration., , , and . IEEE Trans. Parallel Distributed Syst., 29 (9): 2105-2120 (2018)TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks., , , , , , , , , and . MICRO, page 751-765. IEEE, (2020)