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Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1895-1908 (2016)Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms., , , и . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3085-3098 (2015)Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution., , , , , , и . DAC, стр. 71:1-71:6. ACM, (2017)A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration., , , , и . IEEE Comput. Archit. Lett., 15 (2): 69-72 (2016)A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection., , , , и . IEEE J. Solid State Circuits, 55 (2): 505-519 (2020)Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning., , , , , , , , и . IEEE J. Solid State Circuits, 57 (10): 3164-3178 (2022)A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction., , , , , , , и . IEEE J. Solid State Circuits, 57 (5): 1542-1557 (2022)A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems., , , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1771-1784 (2019)Efficient Scheduling of Irregular Network Structures on CNN Accelerators., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 3408-3419 (2020)SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (10): 4014-4027 (2022)