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Disambiguation of "Ren, Haoxing"

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AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.

, , , , , , , , , and . ISPD, page 175-183. ACM, (2022)

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Jianxin Ren

Zhongliang Ren

Hongming Ren

Jun Ren

Xiaofeng Ren

 

Other publications of authors with the same name

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization., , , , , and . DAC, page 453-458. IEEE, (2007)The nuts and bolts of physical synthesis., , , , , , , , and . SLIP, page 89-94. ACM, (2007)ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5083-5096 (2020)Verifying High-Level Latency-Insensitive Designs with Formal Model Checking., , , , , , and . CoRR, (2021)VerilogEval: Evaluating Large Language Models for Verilog Code Generation., , , and . CoRR, (2023)Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training., , , , , , , and . CoRR, (2022)MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification., , , , , and . DATE, page 1825-1828. IEEE, (2021)Enabling Scalable AI Computational Lithography with Physics-Inspired Models., and . ASP-DAC, page 715-720. ACM, (2023)Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk)., , , and . ICCAD, page 70:1-70:4. IEEE, (2020)Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation., , , and . ICCAD, page 1-8. IEEE, (2023)