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Disambiguation of "Matsumoto, Takeshi"

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An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging.

, , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (7): 1519-1529 (2011)

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Takeshi Morita

Dairi Matsumoto

Koichi Matsumoto

Takeshi Morita

Teijiro Matsumoto

 

Other publications of authors with the same name

Hardware implementation of BLTL property checkers for acceleration of statistical model checking., , and . ICCAD, page 670-676. IEEE, (2013)Hybrid world object tracking for a virtual teaching agent., , , , , , and . IJCNN, page 1-9. IEEE, (2010)Experimental Study of Ankle Joint Pushing Mechanism Concerning About the Horizontal Movement of Talus., , and . J. Robotics Mechatronics, 29 (2): 299-305 (2017)FOF: Functionally Observable Fault and its ATPG techniques., , and . VLSI-SoC, page 108-111. IEEE, (2013)A debugging method for gate level circuit designs by introducing programmability., , and . VLSI-SoC, page 78-83. IEEE, (2013)Application of search algorithms to natural language processing., , and . ALTA, page 22-29. Australasian Language Technology Association, (2003)SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions., , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2012)Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging., , and . ICCD, page 402-408. IEEE Computer Society, (2010)Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis., , and . HLDVT, page 162-169. IEEE Computer Society, (2006)Multi-Level Bounded Model Checking with Symbolic Counterexamples., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (2): 696-705 (2011)