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An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging.

, , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (7): 1519-1529 (2011)

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Ultra-low-power voice trigger for wearable devices., , , , , , , , and . ICCE-TW, page 76-77. IEEE, (2015)Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging., , and . ICCD, page 402-408. IEEE Computer Society, (2010)A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures., , , , , , , , and . CGO, page 197-209. ACM, (2017)On-chip dynamic signal sequence slicing for efficient post-silicon debugging., , and . ASP-DAC, page 719-724. IEEE, (2011)AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognition., , , , , , , and . DATE, page 1495-1500. IEEE, (2019)Scalable radio processor architecture for modern wireless communications., , , , and . FPT, page 310-313. IEEE, (2014)An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (7): 1519-1529 (2011)Online Speech Dereverberation Using RLS-WPE Based on a Full Spatial Correlation Matrix Integrated in a Speech Enhancement System., , , , , and . IWAENC, page 36-40. IEEE, (2018)A Post-Silicon Debug Support Using High-Level Design Description., , , and . Asian Test Symposium, page 137-142. IEEE Computer Society, (2009)