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Disambiguation of "Tsukamoto, Sanroku"

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A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration.

, , , and . IEICE Trans. Electron., 95-C (6): 1026-1034 (2012)

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Masaji Tsukamoto

Masaaki Tsukamoto

Nobuko Ohashi Tsukamoto

 

Other publications of authors with the same name

A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration., , , and . IEEE Trans. Biomed. Circuits Syst., 4 (6): 410-416 (2010)A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2456-2462 (2010)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)A 6b 3GS/s flash ADC with background calibration., , , and . CICC, page 283-286. IEEE, (2009)A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS., , , , and . IEEE J. Solid State Circuits, 49 (3): 673-682 (2014)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (12): 3258-3267 (2013)A dynamic offset control technique for comparator design in scaled CMOS technology., , , , , , , and . CICC, page 495-498. IEEE, (2008)Advances in Analog-to-Digital Converters over the Last Decade.. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (2): 524-533 (2017)A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI., , , , , and . IEEE J. Solid State Circuits, 31 (11): 1831-1836 (1996)A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2600-2608 (2010)