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Optimal design of dummy ball array in wafer level package to improve board level thermal cycle reliability (BLR)., , , , , , , , , and 1 other author(s). IRPS, page 3. IEEE, (2018)SRAM stability design comprehending 14nm FinFET reliability., , , , , and . IRPS, page 13. IEEE, (2015)Systematical study of 14nm FinFET reliability: From device level stress to product HTOL., , , , , , , , , and 3 other author(s). IRPS, page 2. IEEE, (2015)Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology., , , , , , , , , and 3 other author(s). IRPS, page 1-5. IEEE, (2020)Reliability of Industrial grade Embedded-STT-MRAM., , , , , , , , , and 21 other author(s). IRPS, page 1-3. IEEE, (2020)Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit., , , , , and . IRPS, page 1-5. IEEE, (2019)Reliability characterization of advanced CMOS image sensor (CIS) with 3D stack and in-pixel DTI., , , , , , , , , and 10 other author(s). IRPS, page 3. IEEE, (2018)The Characterization of Degradation on various SiON pMOSFET transistors under AC/DC NBTI stress., , , , , , , , and . IRPS, page 1-4. IEEE, (2021)Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology., , , , , , , , , and 8 other author(s). IRPS, page 1-5. IEEE, (2020)Effects of Far-BEOL anneal on the WLR and product reliability characterization of FinFET process technology., , , , , , , , , and 1 other author(s). IRPS, page 6. IEEE, (2018)