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A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings.

, , , and . J. Parallel Distributed Comput., 62 (5): 865-884 (2002)

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Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 301-316. Springer, (2006)An approach to test synthesis from higher level., and . Integr., 26 (1-2): 101-116 (1998)A cost optimal parallel algorithm for weighted distance transforms., , , and . Parallel Comput., 25 (4): 405-416 (1999)A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings., , , and . J. Parallel Distributed Comput., 62 (5): 865-884 (2002)Fast false path identification based on functional unsensitizability using RTL information., , , and . ASP-DAC, page 660-665. IEEE, (2009)Secure scan design using shift register equivalents against differential behavior attack., , and . ASP-DAC, page 818-823. IEEE, (2011)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , and . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths., , , , and . IEICE Trans. Inf. Syst., 88-D (8): 1940-1947 (2005)A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification., , and . IEICE Trans. Inf. Syst., 93-D (7): 1857-1865 (2010)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., and . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)