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Disambiguation of "Fujiwara, Hideo"

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A cost optimal parallel algorithm for weighted distance transforms.

, , , and . Parallel Comput., 25 (4): 405-416 (1999)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

System-on-chip test scheduling with reconfigurable core wrappers., and . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)Effect of BIST Pretest on IC Defect Level., , and . IEICE Trans. Inf. Syst., 89-D (10): 2626-2636 (2006)A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification., , and . IEICE Trans. Inf. Syst., 93-D (7): 1857-1865 (2010)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., and . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design., , and . IEICE Trans. Inf. Syst., 94-D (7): 1430-1439 (2011)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , and . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths., , , , and . IEICE Trans. Inf. Syst., 88-D (8): 1940-1947 (2005)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., and . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)