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Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.

, , , , and . IEICE Trans. Inf. Syst., 88-D (8): 1940-1947 (2005)

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Reduced Latch Count Shift Registers.. J. Electron. Test., 11 (2): 183-185 (1997)On-Chip Weighted Random Patterns.. J. Electron. Test., 13 (1): 41-50 (1998)Distributed BIST Architecture to Combat Delay Faults.. J. Electron. Test., 16 (4): 369-380 (2000)Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory., , and . ITC, page 100-105. IEEE Computer Society, (1985)Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection.. IEEE Trans. Computers, 29 (5): 410-416 (1980)On Random Pattern Test Length., and . IEEE Trans. Computers, 33 (6): 467-474 (1984)Memory Chip BIST Architecture.. Great Lakes Symposium on VLSI, page 384-. IEEE Computer Society, (1999)BIST Pretest of ICs: Risks and Benefits., , and . VTS, page 142-149. IEEE Computer Society, (2006)Skewed-Load Transition Test: Part 1, Calculus.. ITC, page 705-713. IEEE Computer Society, (1992)Random Pattern Testability of Delay Faults., and . ITC, page 263-273. IEEE Computer Society, (1986)