Author of the publication

Experimental Demonstration of An Inversion-Type Ferroelectric Capacitive Memory and its 1 kbit Crossbar Array Featuring High CHCS/CLCS, Fast Speed, and Long Retention.

, , , , , , , and . VLSI Technology and Circuits, page 357-358. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

EdgeFlow: Open-Source Multi-layer Data Flow Processing in Edge Computing for 5G and Beyond., , , , and . CoRR, (2018)Hybrid cooperation for machine-to-machine data collection in hierarchical smart building networks., , , , and . IET Commun., 9 (3): 421-428 (2015)Spectrum Trading Contract Design for UAV Assisted Offloading in Cellular Networks., , , and . ICC, page 1-6. IEEE, (2018)Low-Power and Scalable BEOL-Compatible IGZO TFT eDRAM-Based Charge-Domain Computing., , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 5166-5179 (December 2023)Distributed Multi-Cloud Multi-Access Edge Computing by Multi-Agent Reinforcement Learning., , , , and . IEEE Trans. Wirel. Commun., 20 (4): 2565-2578 (2021)Multi-Layer Radio Network Slicing for Heterogeneous Communication Systems., , , and . IEEE Trans. Netw. Sci. Eng., 7 (4): 2378-2391 (2020)Human Behavior Based Learning Framework for Spectrum Allocation in Downlink CoMP for 5G Networks., , , , and . APCC, page 173-178. IEEE, (2018)Boosting the Memory Window of the BEOL-Compatible MFMIS Ferroelectric/ Anti-Ferroelectric FETs by Charge Injection., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 389-390. IEEE, (2022)First Study of the Charge Trapping Aggravation Induced by Anti-Ferroelectric Switching in the MFIS Stack., , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Record High Active Boron Doping using Low Temperature In-situ CVD: Enabling Sub-5×10-10 Ω-cm2 ρc from Cryogenic (5 K) to Room Temperature., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)