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Experimental Demonstration of An Inversion-Type Ferroelectric Capacitive Memory and its 1 kbit Crossbar Array Featuring High CHCS/CLCS, Fast Speed, and Long Retention.

Z. Zhou, L. Jiao, J. Zhou, Z. Zheng, Y. Chen, K. Han, Y. Kang, and X. Gong. VLSI Technology and Circuits, page 357-358. IEEE, (2022)

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Ewha Kang

Mihyun Kang

Kang Teng

Mujin Kang

Jie Kang

Other publications of authors with the same name

Experimental Demonstration of An Inversion-Type Ferroelectric Capacitive Memory and its 1 kbit Crossbar Array Featuring High CHCS/CLCS, Fast Speed, and Long Retention.Z. Zhou, L. Jiao, J. Zhou, Z. Zheng, Y. Chen, K. Han, Y. Kang, and X. Gong. VLSI Technology and Circuits, page 357-358. IEEE, (2022)Novel Bridge Transmission Line Method for Thin-Film Semiconductors: Modelling, Simulation Verification, and Experimental Demonstration.K. Han, Y. Kang, Y. Chen, and X. Gong. VLSI Technology and Circuits, page 1-2. IEEE, (2023)Thickness-Engineered Extremely-thin Channel High Performance ITO TFTs with Raised S/D Architecture: Record-Low RSD, Highest Moblity (Sub-4 nm TCH Regime), and High VTH Tunability.Y. Kang, K. Han, Y. Chen, and X. Gong. VLSI Technology and Circuits, page 1-2. IEEE, (2023)First Demonstration of BEOL-Compatible Write-Enhanced Ferroelectric-Modulated Diode (FMD): New Possibility for Oxide Semiconductor Memory Devices.L. Jiao, K. Han, Z. Zhou, Z. Zheng, X. Wang, Q. Kong, Y. Kang, J. Zhang, L. Liu, and X. Gong. VLSI Technology and Circuits, page 1-2. IEEE, (2023)Extremely Scaled Bottom Gate a-IGZO Transistors Using a Novel Patterning Technique Achieving Record High Gm of 479.5 μS/μm (VDS of 1 V) and fT of 18.3 GHz (VDS of 3 V).C. Wang, A. Kumar, K. Han, C. Sun, H. Xu, J. Zhang, Y. Kang, Q. Kong, Z. Zheng, Y. Wang and 1 other author(s). VLSI Technology and Circuits, page 294-295. IEEE, (2022)BEOL-compatible Ta/HZO/W Ferroelectric Tunnel Junction with Low Operating Voltage Targeting for Low Power Application.L. Jiao, Z. Zhou, Z. Zheng, Y. Kang, C. Sun, Q. Kong, X. Wang, D. Zhang, G. Liu, L. Liu and 1 other author(s). ICICDT, page 5-7. IEEE, (2022)Grain Size Reduction of Ferroelectric HZO Enabled by a Novel Solid Phase Epitaxy (SPE) Approach: Working Principle, Experimental Demonstration, and Theoretical Understanding.D. Zhang, J. Wu, Q. Kong, Z. Zhou, L. Liu, K. Han, C. Sun, X. Wang, G. Liu, L. Jiao and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)First Demonstration of BEOL-Compatible MFMIS Fe-FETs with 3D Multi-Fin Floating Gate: In-situ ALD-deposited MFM, LCH of 50 nm, > 2×109 Endurance, and 58.3% Area Saving.X. Wang, Z. Zheng, Q. Kong, L. Jiao, K. Han, C. Sun, Z. Zhou, L. Liu, Y. Kang, G. Liu and 2 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Disambiguation of "Kang, Yuye"