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Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (3): 410-422 (2010)Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (3): 338-345 (2007)Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (5): 706-710 (May 2023)Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch., , , , , , and . ASICON, page 1-4. IEEE, (2021)Low-Energy Acceleration of Binarized Convolutional Neural Networks Using a Spin Hall Effect Based Logic-in-Memory Architecture., , , , and . IEEE Trans. Emerg. Top. Comput., 9 (2): 928-940 (2021)Contention reduced/conditional discharge flip-flops for level conversion in CVS systems., , and . ISCAS (2), page 669-672. IEEE, (2004)A low-power clock frequency multiplier., , and . ISCAS, IEEE, (2006)On the isomorphism of expressions., and . Inf. Process. Lett., 74 (3-4): 97-102 (2000)A Double-Edge Implicit-Pulsed Level Convert Flip-Flop., , , and . ISVLSI, page 141-144. IEEE Computer Society, (2004)High-performance and low-power conditional discharge flip-flop., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (5): 477-484 (2004)