Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

Y. Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (4): 748-761 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

David Tse-chien Pan

Z Taufig

Xiaoqing Pan

Petra Pan

Pan Li

Other publications of authors with the same name

Global Routing.M. Cho, and D. Pan. Encyclopedia of Algorithms, (2016)On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.K. Shamsi, T. Meade, M. Li, D. Pan, and Y. Jin. IEEE Trans. Inf. Forensics Secur., 14 (2): 347-359 (2019)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.B. Yu, X. Xu, J. Gao, Y. Lin, Z. Li, C. Alpert, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)Skew Management of NBTI Impacted Gated Clock Trees.A. Chakraborty, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 918-927 (2013)Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization.K. Yuan, J. Yang, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 185-196 (2010)MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.Y. Lin, B. Yu, X. Xu, J. Gao, N. Viswanathan, W. Liu, Z. Li, C. Alpert, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1237-1250 (2018)Redundant Local-Loop Insertion for Unidirectional Routing.X. Xu, Y. Lin, M. Li, J. Ou, B. Cline, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (7): 1113-1125 (2017)Semisupervised Hotspot Detection With Self-Paced Multitask Learning.Y. Chen, Y. Lin, T. Gai, Y. Su, Y. Wei, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (7): 1511-1523 (2020)OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions.S. Roy, D. Liu, J. Singh, J. Um, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (10): 1618-1629 (2016)Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks.J. Chen, M. Alawieh, Y. Lin, M. Zhang, J. Zhang, Y. Guo, and D. Pan. IEEE Access, (2020)

BibSonomy

Disambiguation of "Pan, David Z."

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

Please choose a person to relate this publication to

David Tse-chien Pan

Z Taufig

Xiaoqing Pan

Petra Pan

Pan Li

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Pan, David Z."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

Please choose a person to relate this publication to

David Tse-chien Pan

Z Taufig

Xiaoqing Pan

Petra Pan

Pan Li

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.