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Gate Leakage Impact on Full Open Defects in Interconnect Lines., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)ETS 2016 foreword., , , , и . ETS, стр. 1. IEEE, (2016)NIM- a noise index model to estimate delay discrepancies between silicon and simulation., , , , , и . DATE, стр. 1373-1376. IEEE Computer Society, (2010)Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (2): 301-312 (2013)Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality., , , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)Time-dependent Behaviour of Full Open Defects in Interconnect Lines., , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)Full Open Defects in Nanometric CMOS., , , , , и . VTS, стр. 119-124. IEEE Computer Society, (2008)On Performance Testing with Path Delay Patterns., , и . VTS, стр. 29-34. IEEE Computer Society, (2007)Defect Oriented Testing for Analog/Mixed-Signal Designs., , , , , , и . IEEE Des. Test Comput., 29 (5): 72-80 (2012)Power Supply Noise in Delay Testing., , , , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2006)