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Disambiguation of "Figueras, Joan"

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Gate Leakage Impact on Full Open Defects in Interconnect Lines.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)

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Urania Joannou

Demetrios Joannou

Franz-Ruthard Joans

Andra Daniela Joanette

Heinz Joannou

 

Other publications of authors with the same name

Bridging defects resistance in the metal layer of a CMOS process., , and . J. Electron. Test., 8 (1): 35-46 (1996)On Maximizing the Coverage of Catastrophic and Parametric Faults., and . J. Electron. Test., 16 (3): 251-258 (2000)Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (8): 1386-1395 (2016)Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1911-1922 (2011)Experimental Characterization of CMOS Interconnect Open Defects., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 123-136 (2008)An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family., , , and . J. Electron. Test., 16 (3): 289-299 (2000)Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours., , , and . J. Electron. Test., 20 (2): 143-153 (2004)A Discussion on Test Pattern Generation for FPGA - Implemented Circuits., , , , and . J. Electron. Test., 17 (3-4): 283-290 (2001)IDDQ testing: state of the art and future trends., , , , and . Integr., 26 (1-2): 167-196 (1998)New reliability mechanisms in memory design for sub-22nm technologies., , , , , , , , , and 7 other author(s). IOLTS, page 111-114. IEEE Computer Society, (2011)