( en | de | ru )

 

Disambiguation of "Arumí, Daniel"

Author of the publication

copydeleteadd this publication to your clipboard
Gate Leakage Impact on Full Open Defects in Interconnect Lines.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Daniel

Daniel

Daniel Stanze

Systematische Analyse von Rezeptoren und Effektormechanismen der pulmonalen angeborenen Immunität. Uni Marburg, (2009)

Daniel Wied

Zivilprozessuale Qualifikationsprobleme im Spannungsfeld von Vertrag und Delikt: ein Beitrag zur Auslegung nationalen Zivilprozessrechts in europäischer Perspektive. Uni Regensburg, (2009)

Daniel Dirkmann

In-vitro-Untersuchungen zum Effekt von Hypothermie und Azidose auf Variablen thrombelastometrischer Messungen der Blutgerinnung. Uni Duisburg-Essen, (2009)
 

Other publications of authors with the same name

Gate Leakage Impact on Full Open Defects in Interconnect Lines., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1739-1748 (2016)Post-bond test of Through-Silicon Vias with open defects., , and . ETS, page 1-6. IEEE, (2014)True Random Number Generator Based on the Variability of the High Resistance State of RRAMs., , , , , , , and . IEEE Access, (2023)Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1911-1922 (2011)Experimental Characterization of CMOS Interconnect Open Defects., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 123-136 (2008)Defective behaviours of resistive opens in interconnect lines., , and . ETS, page 28-33. IEEE Computer Society, (2005)Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (2): 301-312 (2013)Pre-bond testing of weak defects in TSVs., , and . IOLTS, page 31-36. IEEE, (2014)RRAM based cell for hardware security applications., , and . IVSW, page 1-6. IEEE, (2016)