( en | de | ru )

 

Disambiguation of "Jung, Seong-Ook"

Author of the publication

copydeleteadd this publication to your clipboard
A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With VOH Drift Control.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (6): 1822-1826 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

 

Other publications of authors with the same name

A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface., , and . IEEE Trans. Consumer Electronics, 56 (4): 2400-2405 (2010)An MTJ-based non-volatile flip-flop for high-performance SoC., , , , , and . I. J. Circuit Theory and Applications, 42 (4): 394-406 (2014)MTJ based non-volatile flip-flop in deep submicron technology., , , , , and . ISOCC, page 424-427. IEEE, (2011)Pseudo NMOS based sense amplifier for high speed single-ended SRAM., , , , and . ICECS, page 331-334. IEEE, (2014)Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (10): 2413-2422 (2019)Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 752-765 (2015)Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (11): 2748-2752 (2015)Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (3): 895-898 (2008)Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2737-2747 (2017)SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (8): 2063-2072 (2017)