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Disambiguation of "Yin, Shouyi"

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Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM.

, , and . DAC, page 84:1-84:6. ACM, (2017)

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Shouyi Zhang

Shouyi Zhang

Renfu Yin

Lu Yin

Li Yin

 

Other publications of authors with the same name

Constructing Concurrent Data Structures on FPGA with Channels., , , , and . FPGA, page 172-177. ACM, (2019)Reconfigurable Architecture for Neural Approximation in Multimedia Computing., , , , and . IEEE Trans. Circuits Syst. Video Techn., 29 (3): 892-906 (2019)Towards Efficient Compact Network Training on Edge-Devices., , , and . ISVLSI, page 61-67. IEEE, (2019)A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures., , , , , and . ASP-DAC, page 48-53. IEEE, (2015)An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video., , , , , and . Sci. China Inf. Sci., 56 (7): 1-14 (2013)Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints., , , , , and . Sci. China Inf. Sci., 58 (8): 1-14 (2015)MapReduce inspired loop mapping for coarse-grained reconfigurable architecture., , , and . Sci. China Inf. Sci., 57 (12): 1-14 (2014)Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution., , , , and . IEEE Comput. Archit. Lett., 17 (2): 147-150 (2018)An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS., , , , , , and . VLSI Circuits, page 37-38. IEEE, (2018)A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)., , , , and . FPGA, page 270. ACM, (2015)