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Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.

Y. Lu, L. Liu, Y. Deng, J. Weng, Z. Li, C. Deng, and S. Wei. DAC, page 71:1-71:6. ACM, (2017)

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Liu Liu

Thomas Leibohm

Yeshayahu Leibowitz

Other publications of authors with the same name

A reconfigurable multi-processor SoC for media applications.M. Zhu, L. Liu, S. Yin, Y. Wang, W. Wang, and S. Wei. ISCAS, page 2011-2014. IEEE, (2010)An efficient hardware design for cerebellar models using approximate circuits: special session paper.H. Jiang, L. Liu, and J. Han. CODES+ISSS, page 31:1-31:2. ACM, (2017)A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only).J. Wang, L. Liu, J. Zhu, S. Yin, and S. Wei. FPGA, page 270. ACM, (2015)An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS.S. Yin, P. Ouyang, J. Yang, T. Lu, X. Li, L. Liu, and S. Wei. VLSI Circuits, page 37-38. IEEE, (2018)Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.L. Liu, B. Wang, C. Deng, M. Zhu, S. Yin, and S. Wei. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3081-3094 (2018)Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning.D. Liu, S. Yin, G. Luo, J. Shang, L. Liu, S. Wei, Y. Feng, and S. Zhou. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (12): 2271-2283 (2019)Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.J. Gu, S. Yin, L. Liu, and S. Wei. IEEE Trans. Parallel Distributed Syst., 29 (9): 2105-2120 (2018)TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks.H. Mo, L. Liu, W. Hu, W. Zhu, Q. Li, A. Li, S. Yin, J. Chen, X. Jiang, and S. Wei. MICRO, page 751-765. IEEE, (2020)ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration.F. Tu, Y. Wang, Z. Wu, L. Liang, Y. Ding, B. Kim, L. Liu, S. Wei, Y. Xie, and S. Yin. IEEE J. Solid State Circuits, 58 (1): 243-255 (2023)An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention.Y. Wang, Y. Qin, D. Deng, J. Wei, Y. Zhou, Y. Fan, T. Chen, H. Sun, L. Liu, S. Wei and 1 other author(s). IEEE J. Solid State Circuits, 58 (1): 227-242 (2023)

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Disambiguation of "Liu, Leibo"

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Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Thomas Leibohm

Yeshayahu Leibowitz

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liu, Leibo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Thomas Leibohm

Yeshayahu Leibowitz

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.