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Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem.

, , , , , and . VEHITS, page 59-69. SciTePress, (2018)

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Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis., , , , , , and . Int. J. Embed. Real Time Commun. Syst., 2 (3): 1-20 (2011)Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model., , , , and . ACM Trans. Embed. Comput. Syst., 16 (1): 26:1-26:26 (2016)Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs., , , , , , and . IEEE Embed. Syst. Lett., 11 (3): 93-96 (2019)Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables., , and . ISSRE, page 127-137. IEEE, (2020)AMAIX: A Generic Analytical Model for Deep Learning Accelerators., , , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 36-51. Springer, (2020)Split-cost communication model for improved MPSoC application mapping., , , , and . ISSoC, page 1-8. IEEE, (2013)Retargetable compiler technology for embedded systems - tools and applications., and . Kluwer, (2001)Combined MPSoC Task Mapping and Memory Optimization for Low-Power., , , and . APCCAS, page 121-124. IEEE, (2019)An optimal allocation of memory buffers for complex multicore platforms., , , and . J. Syst. Archit., (2016)Time-constrained code compaction for DSPs., and . IEEE Trans. Very Large Scale Integr. Syst., 5 (1): 112-122 (1997)