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Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation., , , , , и . DATE, стр. 707-710. IEEE, (2021)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , и 2 other автор(ы). DAC, стр. 13. ACM, (2019)Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs., , , , , , , и . ISLPED, стр. 1-6. IEEE, (2021)Analyzing the Electromigration Challenges of Computation in Resistive Memories., , , , и . ITC, стр. 534-538. IEEE, (2022)STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes., , , , , , , , и . ESSDERC, стр. 97-100. IEEE, (2023)Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications., , , , , , и . ISCAS, стр. 1-5. IEEE, (2023)STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application., , , , , , , , , и 6 other автор(ы). IMW, стр. 1-4. IEEE, (2021)A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs., , , , , , , , , и . ICCD, стр. 255-263. IEEE, (2019)Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress)., , , , , и . MPLR, стр. 158-164. ACM, (2023)Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications., , , , , , , , , и . ESSDERC, стр. 275-278. IEEE, (2021)