( en | de | ru )

 

Disambiguation of "Hu, Jiang"

Author of the publication

copydeleteadd this publication to your clipboard
Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES.

, , , , and . CoRR, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jun Hu

Zaijun Hu

Hu Wang

Bing Hu

Ruguo Hu

 

Other publications of authors with the same name

A review of 20 years of naive tests of significance for high-dimensional mean vectors and covariance matrices, and . (2016)cite arxiv:1603.01003.Buffer insertion with adaptive blockage avoidance., , , and . ISPD, page 92-97. ACM, (2002)Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects., and . ISQED, page 80-86. IEEE, (2011)Simultaneous Wireless Information and Power Transfer in Cellular Two-Way Relay Networks With Massive MIMO., , , , , and . IEEE Access, (2018)DUCER: a Fast and Lightweight Error Correction Scheme for In-Vehicle Network Communication., , , and . ICVES, page 1-6. IEEE, (2018)Zero skew clock routing in X-architecture based on an improved greedy matching algorithm., , , , and . Integr., 41 (3): 426-438 (2008)Central Limit Theorem for Mutual Information of Large MIMO Systems With Elliptically Correlated Channels., , and . IEEE Trans. Inf. Theory, 65 (11): 7168-7180 (2019)Boostable Repeater Design for Variation Resilience in VLSI Interconnects., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (9): 1619-1631 (2013)Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (3): 439-443 (2009)Low Power Gated Clock Tree Driven Placement., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (2): 595-603 (2008)