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Disambiguation of "Li, Sih-Han"

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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.

, , , , , , , , , , , , , , , , , , , , and . ISSCC, page 250-252. IEEE, (2021)

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Li Han

Han Li

Han-lin Li

Benea Sih

Kurt Sihling

 

Other publications of authors with the same name

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 196-207 (January 2024)Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 57 (2): 609-624 (2022)Circuit Design Challenges in Computing-in-Memory for AI Edge Devices., , , , , , , , , and 1 other author(s). ASICON, page 1-4. IEEE, (2019)A 1280 x 720 Micro-LED Display Driver with 10-Bit Current-Mode Pulse Width Modulation., , , , , , , , , and 1 other author(s). A-SSCC, page 1-3. IEEE, (2021)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips., , , , , , , , , and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices., , , , , , , , , and 7 other author(s). ISSCC, page 126-127. IEEE, (2023)An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology., , , , , , , , , and 5 other author(s). VLSI Technology and Circuits, page 262-263. IEEE, (2022)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)