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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.

J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hung, J. Ren, T. Pan, S. Li, S. Chang, S. Sheu, W. Lo, C. Wu, X. Si, C. Lo, R. Liu, C. Hsieh, K. Tang, and M. Chang. ISSCC, page 250-252. IEEE, (2021)

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Sheu-Sheu Tan

Ming-Shye Sheu

Huey-jen Sheu

Ching-Long Sheu

Sien-Yi Sheu

Other publications of authors with the same name

Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM.T. Chien, L. Chiou, C. Chang, J. Huang, C. Wu, H. Lee, and S. Sheu. IEEE Trans. Circuits Syst. II Express Briefs, 65-II (9): 1234-1238 (2018)A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hong, J. Ren, T. Pan and 15 other author(s). IEEE J. Solid State Circuits, 58 (3): 877-892 (March 2023)A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer.M. Hong, Y. Chang, Y. Hsin, L. Liu, K. Chen, Y. Su, G. Chen, S. Yang, I. Wang, S. Rahaman and 11 other author(s). VLSI Technology and Circuits, page 379-380. IEEE, (2022)A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices.P. Wu, J. Su, Y. Chung, L. Hong, J. Ren, F. Chang, Y. Wu, H. Chen, C. Lin, H. Hsiao and 10 other author(s). ISSCC, page 1-3. IEEE, (2022)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hung, J. Ren, T. Pan and 11 other author(s). ISSCC, page 250-252. IEEE, (2021)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.Z. Zhang, J. Chen, X. Si, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei, Y. Chiu, J. Hong and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.M. Chang, C. Lin, A. Lee, C. Kuo, G. Yang, H. Tsai, T. Chen, S. Sheu, P. Tseng, H. Lee and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)Resistance switching for RRAM applications.F. Chen, H. Lee, Y. Chen, Y. Hsu, L. Zhang, P. Chen, W. Chen, P. Gu, W. Liu, S. Wang and 4 other author(s). Sci. China Inf. Sci., 54 (5): 1073-1086 (2011)A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing.M. Chang, L. Huang, W. Lin, Y. Chiang, C. Kuo, C. Chuang, K. Yang, H. Tsai, T. Chen, and S. Sheu. IEEE J. Solid State Circuits, 51 (11): 2786-2798 (2016)U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory.M. Wu, M. Hong, C. Shih, Y. Chang, Y. Hsin, S. Chiu, K. Chen, Y. Su, C. Wang, S. Yang and 11 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Disambiguation of "Sheu, Shyh-Shyuan"

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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.

Please choose a person to relate this publication to

Sheu-Sheu Tan

Ming-Shye Sheu

Huey-jen Sheu

Ching-Long Sheu

Sien-Yi Sheu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sheu, Shyh-Shyuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.

Please choose a person to relate this publication to

Sheu-Sheu Tan

Ming-Shye Sheu

Huey-jen Sheu

Ching-Long Sheu

Sien-Yi Sheu

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Chicago
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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.