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SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs., , , , , , , , and . IEEE Des. Test, 40 (6): 64-75 (December 2023)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components., , , , , , , , , and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET., , , , , , , , , and 7 other author(s). CICC, page 1-2. IEEE, (2023)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC., , , , , , , , , and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration., , , , , , , , , and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)