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2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS., , , , , , и . ISSCC, стр. 1-3. IEEE, (2015)A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3., , , , , и . ESSCIRC, стр. 379-382. IEEE, (2014)A Fractional-n subsampling PLL based on a digital-to-time converter., , , и . MIPRO, стр. 66-71. IEEE, (2016)A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction., , , и . ESSCIRC, стр. 83-86. IEEE, (2014)A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS., , , и . ESSCIRC, стр. 79-82. IEEE, (2014)A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS., , , , , и . IEEE J. Solid State Circuits, 50 (9): 2025-2036 (2015)A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (9): 2324-2333 (2015)A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS., , , и . ISSCC, стр. 40-41. IEEE, (2010)CMOS low-power transceivers for 60GHz multi Gbit/s communications., , , , , , , , , и 7 other автор(ы). CICC, стр. 1-8. IEEE, (2013)A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS., , и . ISSCC, стр. 492-493. IEEE, (2009)