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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.

K. Chun, Y. Chu, J. Heo, T. Kim, S. Kim, H. Yang, M. Kim, C. Lee, J. Kim, H. Yoon, C. Shin, S. uhn Cha, H. Kim, Y. Kim, K. Kim, Y. Kim, W. Choi, D. Yim, I. Moon, Y. Kim, J. Lee, Y. Choi, Y. Kwon, S. Choi, J. Kim, Y. Park, W. Kang, J. Chung, S. Kim, Y. Ryu, S. Cho, H. Shin, H. Jung, S. Kwon, K. Kang, J. Lee, Y. Song, Y. Kim, E. Kim, K. Ha, K. Kim, S. Hyun, S. Ko, J. Choi, Y. Sohn, K. Park, and S. Jang. ISSCC, page 206-208. IEEE, (2018)

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Soo Kyung Kim

Kyung Ha Bahlig

Kyung-Taek Ha

Soo-Kyung Seo

Kyung-Hyo Ha

Other publications of authors with the same name

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM.C. Lee, J. Lee, K. Kim, J. Heo, J. Baek, G. Cha, D. Moon, D. Lee, J. Park, S. Lee and 13 other author(s). IEEE J. Solid State Circuits, 53 (10): 2906-2916 (2018)A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.K. Ha, L. Kim, S. Bae, K. Park, J. Choi, Y. Jun, and K. Kim. IEEE J. Solid State Circuits, 44 (11): 3146-3162 (2009)A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator.Y. Kim, S. Chung, K. Ha, S. Bae, and L. Kim. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (10): 2495-2503 (2015)A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.K. Chun, Y. Chu, J. Heo, T. Kim, S. Kim, H. Yang, M. Kim, C. Lee, J. Kim, H. Yoon and 37 other author(s). ISSCC, page 206-208. IEEE, (2018)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.K. Ha, C. Lee, D. Lee, D. Moon, J. Jang, H. Hwang, H. Chi, J. Park, S. Shin, D. Park and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.T. Oh, H. Chung, J. Park, K. Lee, S. Oh, S. Doo, H. Kim, C. Lee, H. Kim, J. Lee and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth.S. Chung, Y. Kim, K. Ha, S. Bae, J. Lee, and L. Kim. IEEE Trans. Circuits Syst. II Express Briefs, 61-II (3): 153-157 (2014)An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme.J. Seol, Y. Kim, S. Chung, K. Ha, S. Bae, J. Lee, J. Choi, and L. Kim. ISSCC, page 410-411. IEEE, (2013)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.K. Ha, S. Lee, Y. Park, H. Kwon, T. Oh, Y. Sohn, S. Bae, K. Park, J. Lee, C. Lee and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.H. Joo, S. Bae, Y. Sohn, Y. Kim, K. Ha, M. Ahn, Y. Kim, Y. Kim, J. Kim, W. Choi and 7 other author(s). ISSCC, page 314-315. IEEE, (2016)

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Disambiguation of "Ha, Kyung-Soo"