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An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI.

B. Mohammadi, O. Andersson, X. Luo, M. Nouripayam, and J. Rodrigues. A-SSCC, page 229-232. IEEE, (2016)

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Magnus Oskarsson

Paul Andersson

Gunther Andersson

Christina Andersson

Olaf Anderßon

Other publications of authors with the same name

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments.Z. Jelcicová, E. Kasapaki, O. Andersson, and J. Sparsø. IEEE Trans. Very Large Scale Integr. Syst., 32 (1): 150-163 (January 2024)A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs.C. Muller, S. Malkowsky, O. Andersson, B. Mohammadi, J. Sparsø, and J. Rodrigues. VLSI-SoC, page 380-385. IEEE, (2013)An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI.B. Mohammadi, O. Andersson, X. Luo, M. Nouripayam, and J. Rodrigues. A-SSCC, page 229-232. IEEE, (2016)A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks.Z. Jelcicová, E. Kasapaki, O. Andersson, and J. Sparsø. ISCAS, page 1-5. IEEE, (2023)A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS.O. Andersson, B. Mohammadi, P. Meinerzhagen, and J. Rodrigues. ESSCIRC, page 243-246. IEEE, (2014)Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS.O. Andersson, B. Mohammadi, P. Meinerzhagen, A. Burg, and J. Rodrigues. IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (6): 806-817 (2016)Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS.O. Andersson, B. Mohammadi, P. Meinerzhagen, A. Burg, and J. Rodrigues. ESSCIRC, page 197-200. IEEE, (2013)A Neural Network Engine for Resource Constrained Embedded Systems.Z. Jelcicová, A. Mardari, O. Andersson, E. Kasapaki, and J. Sparsø. ACSSC, page 125-131. IEEE, (2020)A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.P. Meinerzhagen, O. Andersson, B. Mohammadi, S. Sherazi, A. Burg, and J. Rodrigues. ESSCIRC, page 321-324. IEEE, (2012)TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing.J. Constantin, A. Dogan, O. Andersson, P. Meinerzhagen, J. Rodrigues, D. Atienza, and A. Burg. VLSI-SoC, page 159-164. IEEE, (2012)

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Disambiguation of "Andersson, Oskar"

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An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI.

Please choose a person to relate this publication to

Magnus Oskarsson

Paul Andersson

Gunther Andersson

Christina Andersson

Olaf Anderßon

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Andersson, Oskar"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI.

Please choose a person to relate this publication to

Magnus Oskarsson

Paul Andersson

Gunther Andersson

Christina Andersson

Olaf Anderßon

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI.