( en | de | ru )

 

Disambiguation of "Wunderlich, Hans-Joachim"

Author of the publication

copydeleteadd this publication to your clipboard
Autonomous Testing for 3D-ICs with IEEE Std. 1687.

, , , and . ATS, page 215-220. IEEE Computer Society, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hans-Joachim Wunderlich

Hans-Joachim Wunderlich

Hans-Joachim Wunderlich

Joachim Wunderlich

Joachim Wunderlich

 

Other publications of authors with the same name

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses., , , , and . ITC, page 1-10. IEEE, (2019)High Defect Coverage with Low-Power Test Sequences in a BIST Environment., , , , and . IEEE Des. Test Comput., 19 (5): 44-52 (2002)GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling., and . DATE, page 879-884. IEEE, (2020)Deterministic logic BIST for transition fault testing., , , and . IET Comput. Digit. Tech., 1 (3): 180-186 (2007)Deterministic BIST with Partial Scan., and . J. Electron. Test., 16 (3): 169-177 (2000)SWIFT: Switch-Level Fault Simulation on GPUs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (1): 122-135 (2019)Hardware-optimal test register insertion., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (6): 531-539 (1998)Built-In Test for Hidden Delay Faults., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1956-1968 (2019)Optimized synthesis techniques for testable sequential circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (3): 301-312 (1992)Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits., and . FTCS, page 36-41. IEEE Computer Society, (1988)