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Disambiguation of "Rocha, Leandro M. G."

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Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.

, , , , , , , , and . ISCAS, page 1-5. IEEE, (2019)

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M G Weller

G M Klump

Leandro Maciel

Leandro Cravero

Leandro Perucchi

 

Other publications of authors with the same name

An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing., , , , , and . ICECS, page 1-4. IEEE, (2020)Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors., , , , , , and . IET Comput. Digit. Tech., 15 (3): 230-240 (2021)A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers., , , , , , and . IEEE Trans. Computers, 71 (2): 349-363 (2022)Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation., , , , , , and . SBCCI, page 1-6. IEEE, (2018)Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing., , , , , , , , and . ISCAS, page 1-5. IEEE, (2019)Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers., , , , and . NEWCAS, page 182-185. IEEE, (2020)Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors., , , , , , and . NEWCAS, page 309-312. IEEE, (2018)Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation., , , , , , and . NEWCAS, page 1-4. IEEE, (2019)A power-predictive environment for fast and power-aware ASIC-based FIR filter design., , , , , and . SBCCI, page 168-173. ACM, (2017)Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers., , , , and . ICECS, page 478-481. IEEE, (2017)