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Effective Logic Synthesis for Threshold Logic Circuit Design.

A. Neutzling, J. Matos, A. Mishchenko, A. Reis, and R. Ribas. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 926-937 (2019)

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Maick Griebenow

Jody Skinner

Mijo Matosevic

Luis Nuno Matos Pimentão

Narciso Matos

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Optimization on cell-library design for digital Application Specific Printed Electronics Circuits.M. Llamas, M. Mashayekhi, J. Carrabina, J. Matos, and A. Reis. PATMOS, page 1-6. IEEE, (2014)Open Cell Library in 15nm FreePDK Technology.M. Martins, J. Matos, R. Ribas, A. Reis, G. Schlinker, L. Rech, and J. Michelsen. ISPD, page 171-178. ACM, (2015)Threshold Logic Synthesis Based on Cut Pruning.A. Neutzling, J. Matos, A. Reis, R. Ribas, and A. Mishchenko. ICCAD, page 494-499. IEEE, (2015)Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.W. Neto, V. Possani, F. Marranghello, J. Matos, A. Reis, and R. Ribas. SBCCI, page 1-6. IEEE, (2018)A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design.J. Matos, A. Neutzling, R. Ribas, and A. Reis. ISPD, page 185-192. ACM, (2015)Efficiently Mapping VLSI Circuits With Simple Cells.J. Matos, J. Carrabina, and A. Reis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 692-704 (2019)A Time-Splitting Tau Method for PDE's: A Contribution for the Spectral Tau Toolbox Library.N. Lima, J. Matos, J. Matos, and P. Vasconcelos. Math. Comput. Sci., 16 (1): 7 (2022)Exact Benchmark Circuits for Logic Synthesis.W. Neto, V. Possani, F. Marranghello, J. Matos, P. Gaillardon, A. Reis, and R. Ribas. IEEE Des. Test, 37 (3): 51-58 (2020)maj-n Logic Synthesis for Emerging Technology.A. Neutzling, F. Marranghello, J. Matos, A. Reis, and R. Ribas. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (3): 747-751 (2020)Effective Logic Synthesis for Threshold Logic Circuit Design.A. Neutzling, J. Matos, A. Mishchenko, A. Reis, and R. Ribas. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 926-937 (2019)

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Disambiguation of "Matos, Jody Maick"

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Effective Logic Synthesis for Threshold Logic Circuit Design.

Please choose a person to relate this publication to

Maick Griebenow

Jody Skinner

Mijo Matosevic

Luis Nuno Matos Pimentão

Narciso Matos

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Matos, Jody Maick"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Effective Logic Synthesis for Threshold Logic Circuit Design.

Please choose a person to relate this publication to

Maick Griebenow

Jody Skinner

Mijo Matosevic

Luis Nuno Matos Pimentão

Narciso Matos

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Effective Logic Synthesis for Threshold Logic Circuit Design.