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Disambiguation of "Ribas, Renato P."

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Effective Logic Synthesis for Threshold Logic Circuit Design.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 926-937 (2019)

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Maristella Ribas

Cesar Ribas Cezar

Renato Hasche

Renato Pasold

Renato Fassbind

 

Other publications of authors with the same name

Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , and . LASCAS, page 227-230. IEEE, (2016)Parallel Combinational Equivalence Checking., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 3081-3092 (2020)Graph-Based Transistor Network Generation Method for Supergate Design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC., , , and . IEEE Trans. Emerg. Top. Comput., 5 (2): 247-259 (2017)Concepção de Circuitos e Sistemas Integrados., , and . RITA, 8 (1): 7-21 (2001)A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 5126-5130 (2022)A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design., , , and . ISPD, page 185-192. ACM, (2015)SwitchCraft: a framework for transistor network design., , , , , and . SBCCI, page 49-53. ACM, (2010)BTI and HCI first-order aging estimation for early use in standard cell technology mapping., , , and . Microelectron. Reliab., 53 (9-11): 1360-1364 (2013)ATMR design by construction based on two-level ALS., , , , and . SBCCI, page 1-6. IEEE, (2023)