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Disambiguation of "Mishchenko, Alan"

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Effective Logic Synthesis for Threshold Logic Circuit Design.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 926-937 (2019)

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Oleksiy Mishchenko

Safwat Alani

Maia Alandjiyska

Yilmaz Alan

Bertold Aland

 

Other publications of authors with the same name

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis., , , , and . DATE, page 1649-1654. IEEE, (2019)m-Inductive Property of Sequential Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (6): 919-930 (2016)Effective Logic Synthesis for Threshold Logic Circuit Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 926-937 (2019)Fast computation of symmetries in Boolean functions.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (11): 1588-1593 (2003)A theory of nondeterministic networks., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 977-999 (2006)Improvements to Technology Mapping for LUT-Based FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (2): 240-253 (2007)NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract)., , , , , , and . BCB, page 623-624. ACM, (2014)Scalable min-register retiming under timing and initializability constraints., , and . DAC, page 534-539. ACM, (2008)A Boolean Paradigm in Multi-Valued Logic Synthesis., and . IWLS, page 173-177. (2002)Incremental ATPG methods for multiple faults under multiple fault models., , , and . ISQED, page 177-180. IEEE, (2015)