%0 Conference Paper %1 conf/vlsic/FujiiTTTKNNNM18 %A Fujii, Taro %A Toi, Takao %A Tanaka, Teruhito %A Togawa, Katsumi %A Kitaoka, Toshiro %A Nishino, Kengo %A Nakamura, Noritsugu %A Nakahara, Hiroki %A Motomura, Masato %B VLSI Circuits %D 2018 %I IEEE %K dblp %P 41-42 %T New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#FujiiTTTKNNNM18 %@ 978-1-5386-4214-6

@inproceedings{conf/vlsic/FujiiTTTKNNNM18, added-at = {2020-12-29T00:00:00.000+0100}, author = {Fujii, Taro and Toi, Takao and Tanaka, Teruhito and Togawa, Katsumi and Kitaoka, Toshiro and Nishino, Kengo and Nakamura, Noritsugu and Nakahara, Hiroki and Motomura, Masato}, biburl = {https://www.bibsonomy.org/bibtex/260ee53de93566a6fea2003b7d4d7ba27/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2018}, ee = {https://doi.org/10.1109/VLSIC.2018.8502438}, interhash = {165bd3cabc2a0c7a590e0a3de628e359}, intrahash = {60ee53de93566a6fea2003b7d4d7ba27}, isbn = {978-1-5386-4214-6}, keywords = {dblp}, pages = {41-42}, publisher = {IEEE}, timestamp = {2024-04-10T15:34:19.000+0200}, title = {New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#FujiiTTTKNNNM18}, year = 2018 }