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Disambiguation of "Motomura, Masato"

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New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications.

, , , , , , , , and . VLSI Circuits, page 41-42. IEEE, (2018)

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Masato Ishizaki

Masato Ikuta

Daniele Masato

 

Other publications of authors with the same name

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner., , , , , , and . HCS, page 1-21. IEEE, (2021)A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations., , , , , , and . MCSoC, page 478-485. IEEE, (2023)Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation., , , , , , , , , and 1 other author(s). ICECS, page 169-172. IEEE, (2013)An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration., , , , and . FCCM, page 264-266. IEEE Computer Society, (1998)Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor., , , , , , , , , and 3 other author(s). FCCM, page 328-329. IEEE Computer Society, (2004)Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces., , , , , , and . ESSCIRC, page 105-108. IEEE, (2016)Foreword., and . VLSI Circuits, page 1-2. IEEE, (2016)Decision Forest Training Accelerator Based on Binary Feature Decomposition., , , , , , and . FCCM, page 215. IEEE, (2023)Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet., , , , , , , , and . ISSCC, page 1-3. IEEE, (2022)Advanced Devices and Architectures., , and . Principles and Structures of FPGAs, Springer, (2018)